Design of a self-reconfiguring interconnection network for fault-tolerant VLSI processor arrays

Journal Article · Fri Mar 31 23:00:00 EST 1989 · IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA)

DOI:https://doi.org/10.1109/24.24572· OSTI ID:5213237

Pateras, S; Rajski, J ^[1]

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1. McGill Univ., Montreal, PQ (Canada)

An interconnection network capable of spontaneously reconfiguring a VLSI processor array upon detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. Strategies involved in testing the fault-tolerant array are also presented.

• OSTI ID: 5213237
• Journal Information: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Reliability; (USA) Vol. 38:1; ISSN 0018-9529; ISSN IEERA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER NETWORKS
COMPUTERIZED SIMULATION
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
ELEMENTS
FAULT TOLERANT COMPUTERS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MONTE CARLO METHOD
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
SEMIMETALS
SILICON
SIMULATION