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On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors

Journal Article · · IEEE Trans. Comput.; (United States)
DOI:https://doi.org/10.1109/12.30846· OSTI ID:5849821
The increasing need for the design of high-performance computers has led to the design of special purpose computers such as array processors. This paper studies the design of fault-tolerant array processors. First, it is shown how hardware redundancy can be employed in the existing structures in order to make them capable of withstanding the failure of some of the array links and processors. Then distributed fault-tolerance schemes are introduced for the diagnosis of the faulty elements, reconfiguration, and recovery of the array. Fault tolerance is maintained by the cooperation of processors in a decentralized form of control without the participation of any type of hardcore or fault-free central controller such as a host computer.
Research Organization:
Wisconsin Univ., Milwaukee, WI (USA). Dept. of Electrical Engineering
OSTI ID:
5849821
Journal Information:
IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:7; ISSN ITCOB
Country of Publication:
United States
Language:
English

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