Fault tolerance for array processors
Book
·
OSTI ID:7081558
Having a large number of processing elements, array processors offer a promising solution to the computational requirements in real-time digital signal processing. From the fault tolerance point of view the regularity and locality of the array processor presents unique advantages as well as new constraints. This dissertation describes the development of a run-time fault-tolerant-wavefront array processor. A systematical method of stopping the processors, diagnosing the faulty elements, and reconfiguring the array is devised. A switch structure is introduced for the reconfiguration of mesh-connected arrays. This architecture offers great flexibility in structuring the array. Errors are detected at run-time by applying dual modular redundancy at each node. When a discrepancy is noted, diagnosis of the faulty processing element can be accomplished using a method of loop testing. Several algorithms for reconfiguration are presented along with reliability calculations and comparisons to other architectures. In addition, a self-healing system is developed that is especially useful for wafer-scale integration. The workload of fault tolerance is distributed over the entire array, thus taking advantage of the parallel processing available. This thesis also investigates a global attack to the problem of embedding an array upon a partially defective one.
- OSTI ID:
- 7081558
- Country of Publication:
- United States
- Language:
- English
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