Parallel/pipeline VLSI computing structures for robotics applications
Many control schemes have been proposed for robotic mechanisms. The combination of Jacobian and inverse plant techniques has been proven to have excellent potential for fast, precise mechanism control. Since, however, such an approach is computation intensive, real time control is difficult to attain. A robotics processor chip (RP), being developed with state-of-the-art VLSI technology, will be the basic building block of a special purpose attached processor. The RPs are designed to be connected in a mesh network to form a parallel-pipelined structure capable of performing all of the vector and matrix computations required for robotic mechanism control in real time. The system throughput, based on this structure, is expected to be considerably greater than that attainable using a commercial attached array processor. The throughput limitation of such array processors arises from the fact that they are designed for the manipulation of large vectors and matrices. When dealing with robotic systems, however, the vector and matrix dimensions usually fall into the range from three to six, with the result that the array processor becomes I/O bound. The RP chip contains a flating point adder and a floating point multiplier. Each of these two independent arithmetic units can operate concurrently and is designed with three pipeline stages.
- Research Organization:
- Ohio State Univ., Columbus (USA)
- OSTI ID:
- 5792560
- Country of Publication:
- United States
- Language:
- English
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