Pipelined distributed arithmetic PFFT processor
Journal Article
·
· IEEE Trans. Comput.; (United States)
A general architecture is described for implementing prime factor fourier transform (PFFT) using distributed arithmetic and look-up tables in ROMs to perform the computations. It is found to be much simpler and more modular than a design that uses multipliers and adders. The architecture is also suitable for computing other linear functions. The implementation of a 504-point PFFT processor with a throughput of 104 khz for complex data points is described. A proposed VLSI implementation of the processor is compared to DFT processors that can be built with currently available VLSI chips.
- Research Organization:
- Univ. of Toronto, Ontario, Canada
- OSTI ID:
- 5199300
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 12; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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