Skip to main content
U.S. Department of Energy
Office of Scientific and Technical Information

Pipeline and parallel-pipeline FFT processors for VLSI implementations

Journal Article · · IEEE Trans. Comput.; (United States)

In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT algorithms in the light of these constraints. In this paper, several methods for computing the FFT in hardware are reviewed. Pipeline structures for the Cooley-Tukey algorithm and the Good prime factor algorithm are presented. The various small base modules required for the construction of these processors are examined with VLSI implementations in mind. For prime bases, an algorithm due to Rader is used which is easier to implement in a pipeline than the minimum multiply algorithms of Winograd. The Winograd technique of centralizing the multiplies of several relatively prime bases is used to develop a pipeline which requires less hardware than pipelines based on the algorithms above. A notation is then presented which allows parallel-pipeline versions of FFT processors to be developed for all of these algorithms. These versions are well suited for use in VLSI implementations due to the efficient use of chip I/O bandwidth between the stages of the FFT algorithms.

OSTI ID:
6084101
Journal Information:
IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-33:5; ISSN ITCOB
Country of Publication:
United States
Language:
English