High-performance VLSI algorithms and architectures for digital signal processing
Results are presented of a unified study of the algorithms, architectures, IC chip design considerations, and figure-of-merit evaluation for the application of very Large Scale Integration (VLSI) technology to high-performance Digital Signal Processing (DSP). Six interrelated areas of research are discussed. The first topic is algorithmic in nature, formalizing a modified version of the Cooley-Tukey Fast Fourier Transform (FFT) Algorithm which enhances its adaptability to VLSI implementation. The next section covers practical research work,describing the architecture, design, and building of VLSI DSP chips based upon FFT formulation. Afterwards, architectures are examined for next-generation signal processors, where the advent of submicron technology will provide for increased computational capabilities. Other research efforts include contributions to design issues. Finally, Thompson's lower bounds for computation of the N-point DFT are derived, but not in the finite field-integer number system as all other researchers have done. Rather, his results are extended by using the complex floating-point number system.
- Research Organization:
- Cornell Univ., Ithaca, NY (USA)
- OSTI ID:
- 7106907
- Country of Publication:
- United States
- Language:
- English
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