High-speed VLSI networks for computing the discrete fourier transform
The authors propose a VLSI design for computing the discrete Fourier transform that can be used to implement the general Winograd algorithm or Good's algorithm when it is based on the Winograd type small n DFTs. The design is simple and makes extensive use of parallelism and pipelining. The corresponding network has two basic memory units: a ROM is used to store the small n algorithms, and a two-dimensional memory of shift registers is used to store the intermediate results. The processing part consists basically of two units: a two-dimensional mesh of adders and a set of multipliers. The control can be implemented in VLSI and it is only slightly more complicated than the one required by FFT. It is shown that the performance of the design is the best possible in a certain sense and that Winograd's algorithm will offer an advantage over FFT in VLSI. 21 references.
- OSTI ID:
- 5082445
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990200* -- Mathematics & Computers
ALGORITHMS
DATA-FLOW PROCESSING
DESIGN
ELECTRONIC CIRCUITS
FOURIER TRANSFORMATION
IMPLEMENTATION
INTEGRAL TRANSFORMATIONS
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PROGRAMMING
SIGNALS
TRANSFORMATIONS