Being stingy with multipliers

Journal Article · Fri Jun 01 04:00:00 EDT 1990 · IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/12.53602· OSTI ID:6637460

Owens, R M; Irwin, M J ^[1]

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1. Pennsylvania State Univ., University Park, PA (USA). Dept. of Computer Science

This paper contends that from an implementation point of view it is often the case that the chip area occupied by a VLSI signal processor is dominated and, therefore, largely determined by the area that must be devoted to multipliers. Therefore, signal processors that have high multiplier utilization (attain a higher throughput for a given number of multipliers) are of interest because it is possible for them to also attain good VLSI area utilization. The authors present several signal processing architectures that have optimal multiplier utilization and compare these architectures to several more conventional alternatives. They also demonstrate how their architectures achieve better multiplier utilization and, hence, VLSI area utilization without suffering a degradation in utilization of other resources (e.g., adders and interconnect).

• OSTI ID: 6637460
• Journal Information: IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Computers (Institute of Electrical and Electronics Engineers); (USA) Vol. 39:6; ISSN ITCOB; ISSN 0018-9340
• Country of Publication: United States
• Language: English

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