On bit sequential multipliers
Conference
·
OSTI ID:5362523
Recently bit sequential multiplier algorithms have been found more useful in the area of interconnection of multiple processors within a VLSI structure. The object of the present paper is to suggest modified bit sequential algorithms to achieve more speed and to attain conformity with other algorithms such as divisions, square-rooting etc. With a view to using them in future arithmetic arrays. The following are considered: a) bit sequential multiplier using carry look-ahead technique, b) bit sequential multiplier using most significant bit first, and c) nega-binary bit sequential multiplier. 10 references.
- OSTI ID:
- 5362523
- Country of Publication:
- United States
- Language:
- English
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