16-bit CMOS/SOS multiplier-accumulator
Conference
·
OSTI ID:5213930
A high speed and low power 16-bit parallel multiplier with an accumulator on a chip, which performs 16-bit*16-bit multiplication and accumulation in 60 ns with 65 mw, is described. The LSI uses a modified array scheme to reduce the number of adding stages of partial products, which requires 9 stages for the 16-bit multiplication and 35-bit accumulation with keeping regularity except for the final carry look-ahead circuits. The use of 2.5 mum CMOS/SOS structure contributes to reductions of the power dissipation, chip area (4.2 mm square) and operation time. 8 references.
- OSTI ID:
- 5213930
- Report Number(s):
- CONF-820908-
- Country of Publication:
- United States
- Language:
- English
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