Canonical bit-sequential multiplier
A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculations of a 2 k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on the number of bits in the product. The internal logic for generating the inputs to the carry-save adders is given. This cell directly accepts the bit-serial inputs and generates a bit-serial output. Longer binary operands can be multiplied by simply cascading identical cells without change to existing cells. A given multiplier can process shorter operands in correspondingly shorter times. Applicability of this technique to VLSI implementation of the basic multiply/add operation useful in signal processing algorithms is described. 14 references.
- Research Organization:
- Texas A and M Univ., College Station
- OSTI ID:
- 5001097
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 8; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
Similar Records
Design and performance of VLSI based parallel multiplier
High speed parallel binary multiplier