High speed parallel binary multiplier
An n x n bit multiplier is described comprising: a shifter having a plurality of inputs, each shifter input for receiving multiple bits of data in a first order and a shifter output for outputting multiple bits of data of one of the shifter inputs in the first order or in a shifted order in response to a shifter control signal; a temporary register having an input coupled to the output of the shifter and an output coupled to first multiplex means; an accumulator having an input coupled to the output of the shifter and an output coupled on an adder; the temporary register and the accumulator alternatively enabled or disabled by a SELREG control signal to receive the output of the shifter; first and second multiplex means for respectively receiving the output of the temporary register and a plurality of other inputs and outputting at least two multiplier operands; a multiplier array for receiving the operands from the first and second multiplex means, and for outputting partial products of the operands; and an adder coupled to the multiplier array for receiving the partial products output from the multiplier and the output of the accumulator for outputting the sum or difference of the adder inputs to an output coupled to one of the inputs of the shifter.
- Assignee:
- Texas Instruments Inc., Dallas, TX
- Patent Number(s):
- US 4809211
- OSTI ID:
- 6384715
- Country of Publication:
- United States
- Language:
- English
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