Pipelineable structure for efficient multiplication and accumulation operations
A pipelineable array multiplier is described for multiplying first and second input operands and providing an output product, the array multiplier utilizing a predetermined recoding algorithm to implement a multiplication operation with X row and Y columns of partial product bits which when summed provide the output product, where X and Y are integers. The array multiplier consists of: X columns of summing means for adding the partial product bits of the array to form the output product, each of the X columns of summing means adding the partial product bits of a predetermined one of the X rows in a time overlapping operation between successive columns and during successive time periods, and each column of summing means except a first selectively coupled to a previous column for receiving partial product input bits from the previous column, each column of summing means comprising a predetermined number of pairs of adder circuits, each pair being series-connected and the predetermined number of pairs of adder circuits in each column being determined by a ratio of carry bit input to output and sum bit input and output propagation delays of the adder circuits when forming output sum and carry bits.
- Assignee:
- Motorola, Inc., Schaumburg, IL
- Patent Number(s):
- US 4843585
- OSTI ID:
- 5590360
- Country of Publication:
- United States
- Language:
- English
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