Pipelined multiply-accumulate unit

Patent · Sun Sep 07 04:00:00 EDT 1986

OSTI ID:5127988

Betz, B K

This patent describes an apparatus for calculating a sum of products of pairs of input numbers, each of the pairs of input numbers including a first member presented as an m bit binary number and a second member presented as a n bit binary number. The apparatus provides a k bit binary number as an output signal at k apparatus output means, where n,m, and k are positive integers. The system comprises: clock conductor line means, basic cell means each of the cell means having a clock input terminal means, signal input terminal means, and q output means, where q is an integer. The clock input terminal means is electrically connected to the clock conductor line means each of the basic cell means being capable of performing an adder operation on signals arriving at the signal input terminal means and further being capable of latching results from the adder operation at the output terminal means upon receipt of a predetermined signal at the clock input terminal means. Each of the basic cell means has cell bit weights being integers in the range of zero to k-1, each of the basic cell signal input terminal means having a device bit weight and array bit weight associated therewith.

• Assignee: Honeywell, Inc., Minneapolis, MN
• Patent Number(s): US 4616330
• OSTI ID: 5127988
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTER ARCHITECTURE
COMPUTER CALCULATIONS
COMPUTER OUTPUT DEVICES
CONDUCTOR DEVICES
CONNECTORS
DATA-FLOW PROCESSING
ELECTRIC CONDUCTORS
ELECTRICAL EQUIPMENT
EQUIPMENT
PROGRAMMING
SIGNALS