Floating-point systolic array including serial processors
Patent
·
OSTI ID:7129241
This patent describes, in a systolic array system utilizing a plurality of semiconductor chips, a semiconductor chip. It comprises: a plurality of processing elements each including a floating-point serial processor and a plurality of data storage registers; global bus means coupled to the serial processor of each of the plurality of processing elements for inputing and outputing data to and from each chip and for programming each serial processor; and a plurality of data buses coupled to each of the plurality of data storage registers of each of the plurality of processing elements. The global bus means being coupled to the plurality of data storage registers for programming the data storage registers.
- Assignee:
- Motorola, Inc., Schaumburg, IL
- Patent Number(s):
- US 4872133
- Application Number:
- PPN: US 7157682A
- OSTI ID:
- 7129241
- Country of Publication:
- United States
- Language:
- English
Similar Records
Reconfigurable processor-array
Design and programming of systolic array cells for signal processing
Multiprocessors on a single semiconductor chip
Book
·
Sat Dec 31 23:00:00 EST 1988
·
OSTI ID:5501499
Design and programming of systolic array cells for signal processing
Thesis/Dissertation
·
Sat Dec 31 23:00:00 EST 1988
·
OSTI ID:5923892
Multiprocessors on a single semiconductor chip
Patent
·
Tue Jul 17 00:00:00 EDT 1990
·
OSTI ID:6541187