Design and programming of systolic array cells for signal processing
This thesis presents a new methodology for the design, simulation, and programming of systolic arrays in which the algorithms and architecture are simultaneously optimized. The algorithms determine the initial architecture, and simulation is used to optimize the architecture. The simulator provides a register-transfer level model of a complete systolic array computation. To establish the validity of this design methodology two novel programmable systolic array cells were designed and programmed. The cells were targeted for applications in high-speed signal processing and associated matrix computations. A two-chip programmable systolic array cell using a 16-bit multiplier-accumulator chip and a semi-custom VLSI controller chip was designed and fabricated. A low chip count allows large arrays to be constructed, but the cell is flexible enough to be a building-block for either one- or two-dimensional systolic arrays. Another more flexible and powerful cell using a 32-bit floating-point processor and a second VLSI controller chip was also designed. It contains several architectural features that are unique in a systolic array cell: (1) each instruction is 32 bits, yet all resources can be updated every cycle, (2) two on-chip interchangeable memories are used, and (3) one input port can be used as either a global or local port. The key issues involved in programming the cells are analyzed in detail. A set of modules is developed which can be used to construct large programs in an effective manner. The utility of this programming approach is demonstrated with several important examples.
- Research Organization:
- Minnesota Univ., Minneapolis, MN (USA)
- OSTI ID:
- 5923892
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
DATA PROCESSING
DESIGN
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MATRICES
MICROELECTRONIC CIRCUITS
OPTIMIZATION
PROCESSING
PROGRAMMING
SIGNALS
SIMULATION
TESTING
USES
VALIDATION