Systolic diagnosis of processor arrays
With the advances in VLSI technology, it has become feasible to implement a multiprocessor system consisting of identical cells on a single chip or on a single wafer. Unfortunately, the realization of such a system is impeded by several difficult technological problems. Of these, probably the most fundamental problem is the high probability of failure of a system of such dimensions. In this thesis, an efficient fault diagnosis method for processor arrays is proposed. The method is based on systolic comparison of array cell functions. In the fault diagnosis, both cells and programmable switches are assumed to fail. The performance of the method is analyzed with respect both to the locatability of fault-free cells and to testing time. Real time applications of the method to homogeneous systems are illustrated. Finally, algorithm level systolic diagnosis for a VLSI sorter and an FF processor is studied. Low hardware and time overhead are shown to be major advantages of the method.
- Research Organization:
- Texas Univ., Austin (USA)
- OSTI ID:
- 6471891
- Country of Publication:
- United States
- Language:
- English
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