Power and ground routing for semi-custom VLSI circuits

Book · Wed Jan 01 04:00:00 EST 1986

OSTI ID:7081543

Chowdhury, S

This thesis deals with the problem of routing power and ground (p/g) nets in integrated circuits composed of logic modules, where the nets are routed in the channels between the modules. The logic modules are assumed to have internal power (ground) networks which are accessible from outside the modules through power (ground) pins on the boundary of the modules. The problem of connecting power (ground) pins on the modules to the power (ground) pads of a chip using only one metal layer is addressed. The Hamiltonian cycles concept is used to enumerate the number of tree topologies for a placement and construct planar tree topologies for p/g nets. An associated problem called construction of local nets for individual modules is solved via two procedures - one for constructing a single pair of local nets, and the other for constructing all possible pairs. The run time complexity of these procedures is studied. The problem of width determination for p/g routes is studied in depth. Various constraints associated with a p/g tree are identified and formulated mathematically. The need for voltage drop constraints is illustrated. Two types of voltage drop constraints are identified and their relationships established.

• OSTI ID: 7081543
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
CONSTRAINTS
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
NETWORK ANALYSIS
VOLTAGE DROP