Automated routing method for VLSI with three interconnection layers
Recently, to the extent allowed by the fabricating technology, approaches have been made to develop an automated router for the multi-layer IC layout design. This thesis examines the VLSI routing problem where three layers are available for interconnection. The author investigates the routing problem in three stages: global routing, power/ground routing, and channel routing. The global routing for the three-interconnection layer model is not much different from that of the two layer model. The global routing problem is studied for two cases: gate array and general cell layout. In the three-layer grid model, power/ground wires keep the direction-per-layer scheme as signal net wires. However, the power/ground routing is further constrained by the width of wires and the layers they are laid on. The major result presented in this dissertation is an algorithm for a channel routing problem. Given a rectangular channel with terminals on top and bottom sides, the algorithm will find a three-layer channel routing that minimizes the channel width and the wire length. Experimental results show that the router is close to optimal.
- Research Organization:
- Iowa State Univ. of Science and Technology, Ames (USA)
- DOE Contract Number:
- W-7405-ENG-82
- OSTI ID:
- 6624895
- Country of Publication:
- United States
- Language:
- English
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