Incremental placement and routing of VLSI macrocells
This dissertation proposes a strategy to automatically position and interconnect a set of rectangular VLSI macrocell blocks by using an integrated set of incremental algorithms. The set of tools is subdivided into three major modules - design manager, floor planner (ExPlan), and global router (MAP). Design manager is used as an interface between the database and the user to simplify the user's task of cell library management by a use of simple command language. ExPlan is used to generate a transformation matrix of given cell list and netlist by best first heuristic search mechanism. The resulting floorplan provides coordinate and orientation of each cell in the cell list with sufficient channel dimension between cells for all nets to be successfully connected and total net lengths minimized. Absolute placement and routing is performed by MAP to create a layout which minimizes overall area by incrementally compacting channels. Each rectangular channel is partitioned such that they can be routed in a predetermined sequence to eliminate the usage of a switchbox router. MAP has capability to route nets with multiple terminals as well as perform connections on standard cells. The final routed result is automatically checked against the netlist for verifying the connectivity of all nets.
- Research Organization:
- South Carolina Univ., Columbia, SC (USA)
- OSTI ID:
- 6089967
- Country of Publication:
- United States
- Language:
- English
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