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Development of a CMOS time memory cell VLSI and CAMAC module with 0. 5 ns resolution

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
OSTI ID:7065689
;  [1];  [2]
  1. National Lab. for High Energy Physics, Tsukuba, Ibaraki (Japan)
  2. NTT LSI Lab. 3-1 Morinosato Wakamiya, Atsugi, Kanagawa 243-01 (Japan)

A CMOS time-to-digital converter chip, the Time Memory Cell (TMC), for high-rate wire chamber application has been developed. The chip has a timing resolution of 0.52 ns, dissipates only 7 mW/channel, and contains 4 channels in a chip. Each channel has 1024 memory locations which act as a buffer 1[mu]s deep. The chip was fabricated in a 0.8 [mu]m CMOS process and is 5.0 mm by 5.6 mm. Using the TMC chip, a CAMAC module with 32 input channels was developed. This module is designed to operate in both 'Common Start' and 'Common Stop' modes. The circuit of the module and test results are described in this paper.

OSTI ID:
7065689
Report Number(s):
CONF-911106--
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 39:4; ISSN 0018-9499; ISSN IETNAE
Country of Publication:
United States
Language:
English

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