Time memory cell VLSI for the PHENIX drift chamber

Journal Article · Mon Jun 01 04:00:00 EDT 1998 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.682626· OSTI ID:624212

Arai, Y; Ikeno, M ^[1]; Sagara, M; Emura, T ^[2]

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1. National High Energy Accelerator Research Organization, Tsukuba, Ibaraki (Japan). Inst. of Particle and Nuclear Studies
2. Tokyo Univ. of Agriculture and Technology, Koganei, Tokyo (Japan)

A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 {micro}sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 {micro}m CMOS gate-array technology.

• OSTI ID: 624212
• Report Number(s): CONF-971147--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 3Pt1 Vol. 45; ISSN 0018-9499; ISSN IETNAE
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
ANALOG-TO-DIGITAL CONVERTERS
BROOKHAVEN RHIC
DRIFT CHAMBERS
INTEGRATED CIRCUITS
READOUT SYSTEMS
TIMING CIRCUITS