Parallel bit-level pipelined VLSI designs for high-speed signal processing

Journal Article · Tue Sep 01 04:00:00 EDT 1987 · Proc. IEEE; (United States)

DOI:https://doi.org/10.1109/PROC.1987.13872· OSTI ID:5938733

Hatamian, M; Cash, G L

This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. The authors discuss issues involved in designing such fully pipelined architectures. These include clock skew, clock distribution networks, buffering, timing simulation, area overhead due to pipelining, and testing. A total of six bit-level pipelined designs, including a multiplier, an FIR filter block, and a multichannel multiply-accumulate/add chip, have now been fabricated in CMOS technology. These chips have been tested both for functionality and speed. The results of these tests and the applications of these chips are presented and discussed.

• Research Organization: AT and T Bell Labs., Holmdel, NJ 07733
• OSTI ID: 5938733
• Journal Information: Proc. IEEE; (United States), Journal Name: Proc. IEEE; (United States) Vol. 75:9; ISSN IEEPA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210 -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERS
DESIGN
DIGITAL COMPUTERS
EFFICIENCY
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
PARALLEL PROCESSING
PERFORMANCE
PLANNING
PROGRAMMING
SIGNAL CONDITIONING
SIGNALS
SUPERCOMPUTERS
TESTING