Large array VLSI filter
Conference
·
OSTI ID:5140669
A 35-by-35-element pipelined convolutional kernel is being fabricated using VLSI chips, each containing a 5-by-1 segment of the kernel. Three levels of printed circuitry are used: the first is used for the VLSI chips; the second connects seven chips on one platform; and the third connects seven platforms with associated delay lines fitting on one board. Therefore, on each board there are seven rows of the kernel containing 245 multipliers and adders, and five such boards complete the kernel array. Each multiplier accepts an 8-bit picture element which is multiplied by a 16-bit weight. A truncated 22-bit product is added to a previously stored product sum and the results are shifted to the following multiplier as the next picture element is read. The multiplier uses a modified booth algorithm to reduce the number of shift add operations nearly in half. The filter box can be connected to any CPU. 3 references.
- OSTI ID:
- 5140669
- Country of Publication:
- United States
- Language:
- English
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