Fermilab Physics Department Fastbus TDC module

Journal Article · Mon Apr 01 04:00:00 EST 1991 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)

DOI:https://doi.org/10.1109/23.289312· OSTI ID:5038900

Cancelo, G; Hansen, S; Cotta-Ramusino, A ^[1]; Hawkey, M; Patti, R ^[2]

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1. Fermi National Accelerator Lab., Batavia, IL (United States)
2. ASIC Designs Inc., Naperville, IL (US)

This paper describes a prototype 64 channel Fastbus TDC built at Fermilab. The module features a full custom CMOS four channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four event deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40,000 events per second with dead time on the order of 15%. The TDC operates in common stop mode with a full scale of 1 {mu}sec and a resolution of 1 nsec.

• OSTI ID: 5038900
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Vol. 38:2; ISSN 0018-9499; ISSN IETNA
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
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46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
ACCELERATORS
CYCLIC ACCELERATORS
DATA ACQUISITION SYSTEMS
DEAD TIME
FASTBUS SYSTEM
FERMILAB ACCELERATOR
OPERATION
SYNCHROTRONS
TIMING PROPERTIES