Fermilab Physics Department Fastbus TDC module

Conference · Mon Jul 01 04:00:00 EDT 1991

OSTI ID:5335199

Cancelo, G; Hansen, S; Cotta-Ramusino, A

A prototype 64 channel Fastbus TDC built at Fermilab is described. The module features a full custom CMOS four channel gated integrator chip. One level of analog buffering at the inputs is implemented on chip. A four event deep output queue at the bus interface allows a high event rate with low dead time. Each channel can record up to two hits per event. With an occupation rate of 10%, the module can operate at 40,000 events per second with dead time on the order of 15%. The TDC operates in common stop mode with a full scale of 1 {mu}sec and a resolution of 1 nsec. 5 refs., 6 figs.

• Research Organization: Fermi National Accelerator Lab., Batavia, IL (United States)
• Sponsoring Organization: DOE; USDOE, Washington, DC (United States)
• DOE Contract Number: AC02-76CH03000
• OSTI ID: 5335199
• Report Number(s): FNAL/C-91/189; CONF-9010220--30; ON: DE91016509
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
43 PARTICLE ACCELERATORS
430303* -- Particle Accelerators-- Experimental Facilities & Equipment
ACCELERATORS
CALIBRATION
COMPUTERS
CYCLIC ACCELERATORS
DATA ACQUISITION SYSTEMS
DESIGN
ELECTRONIC CIRCUITS
FASTBUS SYSTEM
FERMILAB ACCELERATOR
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
SWITCHING CIRCUITS
SYNCHROTRONS