Modeling and simulation of physical faults in CMOS VLSI circuits

Thesis/Dissertation · Fri Jan 01 04:00:00 EST 1988

OSTI ID:6970752

Gobovic, D

This work presents a new technique for modeling and simulating physical faults in CMOS VLSI circuits at the switch level. The technique is derived from the circuit-level analysis of the nonlinear behavior of MOS devices. The principles of graphical techniques, used for the analysis of nonlinear resistive networks, are modified for the analysis of CMOS circuits. Equivalent V-I Characteristics for the CMOS circuits are obtained by applying operators defined by composition tables, which are used for the switch-level fault simulation. A new switch-level circuit model for CMOS circuits is proposed in which the MOS transistor device is described by two types of nonlinear characteristics, one for faulty and one for fault-free operating conditions. The concept of a faulty signal is introduced to represent the output of the faulty circuit, which cannot be expressed as a valid logic level (0 or 1). Application of the proposed technique is considered and illustrated by several examples. The advantage of the method is the increased accuracy of the fault simulation at the switch-level, and the ability of modeling complex faults such as gate-to-drain and gate-to-source shorts, which cannot be covered by existing fault simulators.

• Research Organization: George Washington Univ., Washington, DC (USA)
• OSTI ID: 6970752
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
ELECTRONIC CIRCUITS
FAULT TREE ANALYSIS
FUNCTIONAL MODELS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
NONLINEAR PROBLEMS
SEMICONDUCTOR DEVICES
SIMULATION
SWITCHING CIRCUITS
SYSTEM FAILURE ANALYSIS
SYSTEMS ANALYSIS
TRANSISTOR SWITCHING CIRCUITS
TRANSISTORS