Fault simulation and transistor-level test generation for physical failures in MOS circuits

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:6946111

Shih, H C

Fault collapsing, test generation, and fault simulation were traditionally developed at the gate level based on the stuck at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults that need to be considered in the system so that the effort for test generation and fault simulation can be reduced, two fault-collapsing techniques (inter-gate fault collapsing and intra-gate fault collapsing) for both nMOS and CMOS circuits including line stuck-at faults, transistor stuck-short faults, and transistor stuck open faults are developed in the first part of the research. In the second part, a new methodology is proposed for generating tests at the transistor level for realistic failures including bridging faults, line open faults, transistor stuck open and stuck short faults, and transistor gate to source short and gate to drain short faults in CMOS combinational circuits. In the third part, a new MOS fault simulator, called FAUST, is developed to simulate circuits under realistic physical failures; its fault model includes node short and line open faults as well as stuck at faults. In the fourth part, FAUST is used to identify the problems with tests in some example circuits. It is shown that tests for MOS VLSI circuits will not detect some physical failures, it these tests are derived using only logic level considerations.

• Research Organization: Illinois Univ., Urbana (USA)
• OSTI ID: 6946111
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990220 -- Computers
Computerized Models
& Computer Programs-- (1987-1989)
ANALOG SYSTEMS
ELECTRICAL FAULTS
ELECTRONIC CIRCUITS
FAILURES
FUNCTIONAL MODELS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
RECOMMENDATIONS
SEMICONDUCTOR DEVICES
SIMULATORS
TESTING
TRANSISTORS