FASTBUS Standard Routines implementation for Fermilab embedded processor boards

Conference · Thu Oct 01 04:00:00 EDT 1992

OSTI ID:6970313

Pangburn, J; Patrick, J; Kent, S; Oleynik, G; Pordes, R; Votava, M ^[1]; Heyes, G; Watson, III, W A ^[2]

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1. Fermi National Accelerator Lab., Batavia, IL (United States)
2. Southeastern Universities Research Association, Inc., Newport News, VA (United States). Continuous Electron Beam Accelerator Facility

In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network.

• Research Organization: Fermi National Accelerator Lab., Batavia, IL (United States)
• Sponsoring Organization: DOE; USDOE, Washington, DC (United States)
• DOE Contract Number: AC02-76CH03000
• OSTI ID: 6970313
• Report Number(s): FNAL/C-92/296; CONF-921005--11; ON: DE93004423
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
430303* -- Particle Accelerators-- Experimental Facilities & Equipment
ACCELERATORS
COMPUTER NETWORKS
CYCLIC ACCELERATORS
DATA ACQUISITION SYSTEMS
FASTBUS SYSTEM
FERMILAB COLLIDER DETECTOR
FERMILAB TEVATRON
ON-LINE SYSTEMS
SYNCHROTRONS