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FASTBUS Readout Controller card for high speed data acquisition

Conference ·
OSTI ID:6264395
 [1]; ; ; ;  [2]
  1. Fermi National Accelerator Lab., Batavia, IL (United States) Rio Grande do Sul Univ., Porto Alegre, RS (Brazil). Dept. of Electrical Engineering
  2. Fermi National Accelerator Lab., Batavia, IL (United States)
This article describes a FASTBUS Readout Controller (FRC) for high speed data acquisition in FASTBUS based systems. The controller has two main interfaces: to FASTBUS and to a Readout Port. The FASTBUS interface performs FASTBUS master and slave operations at a maximum transfer rate exceeding 40 MBytes/s. The Readout Port can be adapted for a variety of protocols. Currently, it will be interfaced to a VME bus based processor with a VSB port. The on-board LR33000 embedded processor controls the readout, executing a list of operations download into its memory. It scans the FASTBUS modules and stores the data in a triple port DRAM (TPDRAM), through one of the Serial Access Memory (SAM) ports of the (TPDRAM). Later, it transfers this data to the readout port using the other SAM. The FRC also supports serial communication via RS232 and Ethernet interfaces. This device is intended for use in the data acquisition system at the Collider Detector at Fermilab. 5 refs., 3 figs.
Research Organization:
Fermi National Accelerator Lab., Batavia, IL (United States)
Sponsoring Organization:
DOE; USDOE, Washington, DC (United States)
DOE Contract Number:
AC02-76CH03000
OSTI ID:
6264395
Report Number(s):
FNAL/C-91/290; CONF-911106--21; ON: DE92004637
Country of Publication:
United States
Language:
English

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