The CHI; A new Fastbus interface and processor
Conference
·
· IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)
OSTI ID:6589291
- CERN, Geneva (CH)
This paper reports on the CERN Host Interface (CHI), a family of interfaces to interconnect Fastbus, VMEbus, and external hot computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial interfaces. For efficiency in a data acquisition chain, the CHI-P contains a 1 MByte triple-port memory which allows concurrent access by Fastbus (as master or slave), the host link, and the 4.5 Mips on board processor.
- OSTI ID:
- 6589291
- Report Number(s):
- CONF-900143--
- Conference Information:
- Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA) Journal Volume: 37:2
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
43 PARTICLE ACCELERATORS
430300* -- Particle Accelerators-- Auxiliaries & Components
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
CERN
COMPUTER CODES
DATA ACQUISITION
EFFICIENCY
FASTBUS SYSTEM
INTERFACES
INTERNATIONAL ORGANIZATIONS
MEMORY DEVICES
MONITORING
PARALLEL PROCESSING
PROGRAMMING
TEST FACILITIES
430300* -- Particle Accelerators-- Auxiliaries & Components
99 GENERAL AND MISCELLANEOUS
990200 -- Mathematics & Computers
CERN
COMPUTER CODES
DATA ACQUISITION
EFFICIENCY
FASTBUS SYSTEM
INTERFACES
INTERNATIONAL ORGANIZATIONS
MEMORY DEVICES
MONITORING
PARALLEL PROCESSING
PROGRAMMING
TEST FACILITIES