Enhanced CPU microbranching architecture

Patent · Tue Jan 13 04:00:00 EST 1987

OSTI ID:6919125

Horst, R W; Harris, R L

This patent describes, in a central processing unit for use in data processing systems wherein a microinstruction causes operands to be processed by executing microinstructions in a multilevel time sequence pipeline, an apparatus for performing microbranching, including: first sensing means for determining that a selected one of a plurality of first test conditions, sensed during a first rank of microcode execution and signifying that a first microbranch type should be taken, has been met; second sensing means for determining that a selected one of second test conditions sensed during a second rank of microcode execution, and signifying that a second microbranch type should be taken, has been met. The second rank of microcode execution occurs later in time than the first rank of microcode execution; first indicator means, responsive to the first sensing means, for assuming a first state if the selected test condition has been met and by assuming a second state if the selected test condition has not been met; second indicator means, responsive to the second sensing means for assuming a first state if the selected test condition has been met and by assuming a second state if the selected test condition has not been met.

• Assignee: Tandem Computers, Inc., Cupertino, CA
• Patent Number(s): US 4636943
• OSTI ID: 6919125
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
COMPUTER ARCHITECTURE
COMPUTER CODES
DATA PROCESSING
DATA-FLOW PROCESSING
MEMORY DEVICES
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
TESTING
TIME DEPENDENCE