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U.S. Department of Energy
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Hierarchical composition of VLSI circuits

Thesis/Dissertation ·
OSTI ID:6864091
A transistor level representation for VLSI circuits is presented. This representation is simple but general, technology independent, hierarchical, and maintains connectivity, circuit schematic information, and the information for mask geometry. A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's type ports. Connection is represented explicitly by shared connection points. The ports describe the interface between this cell and other cells. This representation, together with a set of synthesis and analysis rules, enforces the description of strictly legal designs. A file of technology dependent information indicates how to implement each transistor type, interconnect type, and connection point type, as well as how structure types may interact. Cells described in this representation may be composed hierarchically to form larger cells. A working system supporting this hierarchical representation is also described. This system currently supports design rules for nMOS and cMOS/bulk, and has produced chip descriptions that have been both fabricated and tested.
Research Organization:
California Inst. of Tech., Pasadena (USA)
OSTI ID:
6864091
Country of Publication:
United States
Language:
English