Applications of logical-circuit expressions to CMOS VLSI design automation

Thesis/Dissertation · Thu Jan 01 04:00:00 EST 1987

OSTI ID:5702296

Wu, C F.E.

CMOS technology has been recognized as a leading contender for existing VLSI systems, and is projected by industry analysts as being the dominant technology for the next decade. In this thesis, a novel approach for representing CMOS logic circuit networks at the transistor level is proposed. Unlike traditional device-listing approaches that represent only circuit structures, this representation combines structural data with behavioral information, and thus illustrates a way to reduce the difficulty of information transformation between behavioral and structural representations for CMOS circuits. Functional recognition of logic components is an important issue in circuit verification. A new method based on functional expansion and logical-circuit expressions is proposed, and recognition rules are described. The success of logic-component recognition can help other processes such as reverse engineering, which deals with extracting logic-level components from layouts of unknown-function circuits, and the comparison of CMOS transistor schematic networks. Functional recognition enhances the schematic comparison process in that it brings the comparison up to higher levels. Traditional approaches which use graph matching algorithms for CMOS schematic comparison have difficulty in matching circuits with the same function but different topologies.

• Research Organization: Michigan State Univ., East Lansing, MI (USA)
• OSTI ID: 5702296
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
DESIGN
ELECTRONIC CIRCUITS
GRAPHS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
MATHEMATICS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
SEMICONDUCTOR DEVICES
TOPOLOGY
TRANSISTORS