Performance tradeoffs in the hierarchical design of regular VLSI structures

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:7081521

Leung, Y Y.J.

Hierarchical layout is the prevalent design methodology in the computer-aided generation of VLSI circuits. But, the tradeoff of design complexity versus circuit performance among the various design paths of this hierarchy has yet to be fully assessed and compared numerically. This research provides a systematic and quantitative investigation of this tradeoff for regular structures. Systolic array structures, for which regular levels of modularity are well defined, are used as testbed structures. The hierarchical regularity levels in a systolic structure are the transistor, gate, functional device, processing element (PE), and algorithmic levels. The investigation of modularity is pursued along two distinct paths - the bottom-up and top-down approaches. Using the bottom-up approach and standard NMOS design techniques, several PE's are independently designed using the various design energy-points and pathways of the design hierarchy. The top-down approach is applied to the algorithmic and PE levels where chip-wise modularity is desired. The various chip-wise decompositions of an array structure are parameterized by an I/O bottlenecking index (BI). Results obtained from the bottom-up and top-down approaches provide an analysis of several tradeoff parameters.

• Research Organization: Michigan State Univ., East Lansing (USA)
• OSTI ID: 7081521
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
ARRAY PROCESSORS
COMPUTER-AIDED DESIGN
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
SEMICONDUCTOR DEVICES
TRANSISTORS