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Title: Performance measurements of hybrid PIN diode arrays

Conference ·
OSTI ID:6857500
;  [1];  [2]; ;  [3];  [4];  [5]
  1. California Univ., Berkeley, CA (USA). Space Sciences Lab.
  2. Hughes Aircraft Co., El Segundo, CA (USA)
  3. Hughes Aircraft Co., Carlsbad, CA (USA)
  4. Stanford Linear Accelerator Center, Menlo Park, CA (USA)
  5. Micron Semiconductor, Inc., Longwood, FL (USA)

We report on the successful effort to develop hybrid PIN diode arrays and to demonstrate their potential as components of vertex detectors. Hybrid pixel arrays have been fabricated by the Hughes Aircraft Co. by bump bonding readout chips developed by Hughes to an array of PIN diodes manufactured by Micron Semiconductor Inc. These hybrid pixel arrays were constructed in two configurations. One array format having 10 {times} 64 pixels, each 120 {mu}m square, and the other format having 256 {times} 256 pixels, each 30 {mu}m square. In both cases, the thickness of the PIN diode layer is 300 {mu}m. Measurements of detector performance show that excellent position resolution can be achieved by interpolation. By determining the centroid of the charge cloud which spreads charge into a number of neighboring pixels, a spatial resolution of a few microns has been attained. The noise has been measured to be about 300 electrons (rms) at room temperature, as expected from KTC and dark current considerations, yielding a signal-to-noise ratio of about 100 for minimum ionizing particles. 4 refs., 13 figs.

Research Organization:
Stanford Linear Accelerator Center, Menlo Park, CA (USA)
Sponsoring Organization:
DOE/ER
DOE Contract Number:
AC03-76SF00515
OSTI ID:
6857500
Report Number(s):
SLAC-PUB-5211; CONF-900348-5; ON: DE90010308; TRN: 90-015995
Resource Relation:
Conference: 2. international industrial symposium on the super collider, Miami, FL (USA), 14-16 Mar 1990
Country of Publication:
United States
Language:
English