An analog memory integrated circuit for waveform sampling up to 900 MHz
- Stanford Univ., CA (United States)
The potential of switched-capacitor technology for acquiring analog signals in high-energy physics (HEP) applications has been demonstrated in a number of analog memory designs. The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestal and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrate in a 2-[mu]m complementary metal oxide semiconductor (CMOS) process with polysilicon-to-polysilicon capacitors. The measured rms cell response variation in a channel after cell pedestal subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise + distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 6815586
- Report Number(s):
- CONF-931051-; CODEN: IETNAE; TRN: 94-023097
- Journal Information:
- IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Vol. 41:4Pt1; Conference: NSS-MIC '93: nuclear science symposium and medical imaging conference, San Francisco, CA (United States), 30 Oct - 6 Nov 1993; ISSN 0018-9499
- Country of Publication:
- United States
- Language:
- English
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