High-Speed, High-Resolution Analog Waveform Sampling in VLSI Technology
- SLAC National Accelerator Laboratory (SLAC), Stanford, CA (United States)
Switched-capacitor analog memories are well-suited to a number of applications where a continuous digitization of analog signals is not needed. In data acquisition systems based on the use of an analog memory, the input waveforms are sampled and stored at a high rate for a limited period of time, and the analog samples are then retrieved at a lower rate and digitized with a slow ADC before new waveforms are acquired. The advantages of using an analog memory are lower overall power dissipation and cost, higher density and reliability, and potentially superior performance. The analog memory essentially exploits the fact that the sampling and storage of samples in a bank of analog memory cells can be accomplished at a higher rate and with a greater precision than direct digital conversion. This dissertation examines the important components of an analog memory in detail and investigates their use in a number of architectures. The research has led to the design of an analog memory that can acquire analog waveforms at sampling rates of several hundred MHz with a dynamic range and linearity of more than 12 bits, without the need for elaborate calibration and correction procedures. This is accomplished by means of a new memory architecture that results in memory cell pedestals and sampling times that are independent of the signal level, as well as cell gains that are insensitive to component sizes. The write address control for this memory has been realized with an inverter delay chain that provides substantially higher performance with respect to sampling rate and timing accuracy than other published approaches. Based upon the concepts developed in this work, an experimental analog memory was designed and integrated in a 2-μm CMOS process. Extensive measurements of this prototype at sampling rates up to 700 MHz are presented and demonstrate a dynamic range, linearity, offset, and gain accuracy corresponding to a precision of more than 12 bits after a simple dc baseline subtraction. One 32-cell channel in the experimental circuit dissipates only 2 mW from a single 5-V supply.
- Research Organization:
- SLAC National Accelerator Laboratory (SLAC), Stanford, CA (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC)
- DOE Contract Number:
- AC02-76SF00515
- OSTI ID:
- 1454204
- Report Number(s):
- SLAC-R--531
- Country of Publication:
- United States
- Language:
- English
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