An analog memory integrated circuit for waveform acquisition up to 900 MHz
- Stanford Linear Accelerator Center, Menlo Park, CA (United States)
- Stanford Univ., CA (United States). Center for Integrated Systems
The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-{mu}m complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The measured rms cel pedestal variation in a channel after baseline subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.
- Research Organization:
- Stanford Linear Accelerator Center, Menlo Park, CA (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC03-76SF00515
- OSTI ID:
- 10136576
- Report Number(s):
- SLAC-PUB--6402; CONF-931107--36; ON: DE94009020
- Country of Publication:
- United States
- Language:
- English
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