Method and apparatus for selectively delaying an interrupt of a coprocessor
A method is described for a first data processor to coordinate the execution by a second data processor of a single instruction of a selected program, when the single instruction is received by the first processor for execution by the first processor during the processing of the selected program, so that the first and second processors cooperate in a coprocessing system wherein the second processor does not follow the same instruction stream as the first processor, and the first processor may selectively interrupt the second processor during the execution of the single instruction. The method, practiced by the first processor, comprising the steps of: receiving the single instruction; commanding the second processor to execute the received single instruction; the second processor to interrupt the execution of the single instruction; receiving from the second processor an indication that the requested interrupt of the execution of the single instruction must be delayed by the second processor until a selected point in the execution of the single instruction; periodically polling the second processor during the period of the delay to determine when the second processor interrupts the execution of the single instruction; reading the state of the second processor as of the time the second processor interrupted the execution of the single instruction; storing the state of the second processor; interrupting the processing of the selected program; and upon resuming processing of the selected program, selectively restoring the state of the second processor to the stored state whereby the second processor will resume the execution of the single instruction from the selected point in the execution.
- Assignee:
- Motorola, Inc., Schaumburg, IL
- Patent Number(s):
- US 4758950
- OSTI ID:
- 6788472
- Country of Publication:
- United States
- Language:
- English
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