Implementing precise interrupts in pipelined processors

Journal Article · Sun May 01 04:00:00 EDT 1988 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.4607· OSTI ID:6600842

Smith, J E; Pleszkun, A R

This paper describes and evaluates solutions to the precise interrupt problem in pipelined processors. An interrupt is precise if the saved process state corresponds with a sequential model of program execution where one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predecessors have completed. The precise interrupt problem is described, and five solutions are discussed in detail. The first solution forces instructions to complete and modify the process state in architectural order. The other four solutions allow instructions to complete in any order, but additional hardware is used so that a precise state can be restored when an interrupt occurs. All the methods are discussed in the context of a parallel pipeline structure. Simulation results based on the CRAY-1S scalar architecture are used to show that the first solution results in a performance degradation of at least 16 percent. The remaining four solutions offer better performance, and three of them result in as little as a 3 percent performance loss. Several extensions, including vector architectures, virtual memory, and linear pipeline structures, are briefly discussed.

• Research Organization: Dept. of Electrical and Computer Engineering, Univ. of Wisconsin, Madison, WI (US)
• OSTI ID: 6600842
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:5; ISSN ITCOB
• Country of Publication: United States
• Language: English

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