Error recovery in parallel systems of pipelined processors with caches
Conference
·
OSTI ID:98916
- National Taiwan Univ., Taipei (Taiwan, Province of China)
This paper examines the problem of recovering from processor transient faults in pipelined multiprocessor systems. A pipelined machine allows out of order instruction execution and branch prediction to increase performance, thus a precise computation state may not be available. We propose a modified scheme to implement the precise computation state in a pipelined machine. The goal of this research is to implement a checkpointing and rollback for error recovery in a pipelined system based on the technique to achieving precise computation state. Detailed analysis has been performed to demonstrate the effectiveness of this method.
- OSTI ID:
- 98916
- Report Number(s):
- CONF-940856--; CNN: Grant NSC-82-0408-E002-201
- Country of Publication:
- United States
- Language:
- English
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