Instruction issue logic in pipelined supercomputers

Journal Article · Thu Nov 01 04:00:00 EST 1984 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1984.1676375· OSTI ID:6232353

Weiss, S; Smith, J E

Basic principles and design tradeoffs for control of pipelined processors are first discussed. We concentrate on register-register architectures like the CRAY-1 where pipeline control logic is localized to one or two pipeline stages and is referred to as ''instruction issue logic.'' Design tradeoffs are explored by giving designs for a variety of instruction issue methods that represent a range of complexity and sophistication. These vary from the CRAY-1 issue logic to a version of Tomasulo's algorithm, first used in the IBM 360/91 floating point unit. Also studied are Thornton's ''scoreboard'' algorithm used on the CDC 6600 and an algorithm we have devised. To provide a standard for comparison, all the issue methods are used to implement the CRAY-1 scalar architecture. Then, using a simulation model and the Lawrence Livermore Loops compiled with the CRAY Fortran compiler, performance results for the various issue methods are given and discussed.

• Research Organization: Department of Computer Sciences, University of Wisconsin, Madison, WI
• OSTI ID: 6232353
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-33:11; ISSN ITCOB
• Country of Publication: United States
• Language: English

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