Method and apparatus for selectively evaluating an effective address for a coprocessor
This patent describes a coprocessing system comprising first and second data processors, a method for a first processor to coordinate the execution by a second data processor of a selected single instruction of a selected program when the single instruction is received by the first processor for execution by the first processor during the processing of the selected program so that the first and second processors cooperate in a coprocessing system wherein the second processor does not follow the same instruction stream as the first processors. The patent also describes the method practices by the processor, which comprises the steps of: receiving the single instruction; commanding the second processor to execute the received since instructions; reading a response from the second processor indicating a request to selectively evaluate an effective address contained in the single instruction under execution by the second processor; evaluating the selected effective address in the single instruction if the response indicates that the address must be evaluated by the first processor in support of the execution of the single instruction by the second processor; and holding the evaluated selected effective address in support of the execution of the single instruction by the second processor.
- Assignee:
- Motorola Inc., Schaumburg, IL
- Patent Number(s):
- US 4811274
- OSTI ID:
- 6140147
- Country of Publication:
- United States
- Language:
- English
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