Parallel, multiple coprocessor computer architecture having plural execution modes
This patent describes a coprocessor comprising: means, responsive to the control signals, for enabling the coprocessor to respond to instructions and data in one of a plurality of instruction execution modes, the enabling means distinguishing between instruction execution modes wherein the coprocessor responds to instructions and data singularly with respect to others of the coprocessors and wherein the coprocessor responds to instructions and data in parallel with others of the plurality of coprocessor; and means, coupled to the host processor for receiving instructions and data, for executing instructions received with respect to data provided with the instruction and as present in the respective one of the data memories.
- Assignee:
- Advanced Micro Devices, Inc., Sunnyvale, CA
- Patent Number(s):
- US 4809169
- OSTI ID:
- 6134697
- Country of Publication:
- United States
- Language:
- English
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