Parallel, multiple coprocessor computer architecture having plural execution modes
Patent
·
OSTI ID:6134697
This patent describes a coprocessor comprising: means, responsive to the control signals, for enabling the coprocessor to respond to instructions and data in one of a plurality of instruction execution modes, the enabling means distinguishing between instruction execution modes wherein the coprocessor responds to instructions and data singularly with respect to others of the coprocessors and wherein the coprocessor responds to instructions and data in parallel with others of the plurality of coprocessor; and means, coupled to the host processor for receiving instructions and data, for executing instructions received with respect to data provided with the instruction and as present in the respective one of the data memories.
- Assignee:
- Advanced Micro Devices, Inc., Sunnyvale, CA
- Patent Number(s):
- US 4809169
- OSTI ID:
- 6134697
- Country of Publication:
- United States
- Language:
- English
Similar Records
Control of multiple processors executing in parallel regions
Method and apparatus for selectively evaluating an effective address for a coprocessor
Parallel digital processor
Patent
·
Tue May 09 00:00:00 EDT 1989
·
OSTI ID:5818574
Method and apparatus for selectively evaluating an effective address for a coprocessor
Patent
·
Mon Mar 06 23:00:00 EST 1989
·
OSTI ID:6140147
Parallel digital processor
Patent
·
Mon Feb 12 23:00:00 EST 1990
·
OSTI ID:6893710