IBM RISC System/6000 processor architecture

Journal Article · Sun Dec 31 23:00:00 EST 1989 · IBM Journal of Research and Development (International Business Machines); (USA)

DOI:https://doi.org/10.1147/rd.341.0023· OSTI ID:6764509

Oehler, R R ^[1]; Groves, R D ^[2]

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1. International Business Machines Corp., Yorktown Heights, NY (USA). Thomas J. Watson Research Center
2. IBM Advanced Workstations Div., Austin, TX (US)

This paper describes the hardware architecture of the IBM RISC System/6000 processor, which combines basic RISC principles with a partitioning of registers by function into multiple ALUs. This allows a high degree of parallelism in execution and permits a compiler to generate highly optimized code to manage the interaction among parallel functions. Floating-point arithmetic is integrated into the architecture, and floating-point performance is comparable to that of many vector processors.

• OSTI ID: 6764509
• Journal Information: IBM Journal of Research and Development (International Business Machines); (USA), Journal Name: IBM Journal of Research and Development (International Business Machines); (USA) Vol. 34:1; ISSN IBMJA; ISSN 0018-8646
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER CALCULATIONS
COMPUTER CODES
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OPTIMIZATION
PARALLEL PROCESSING
PERFORMANCE
PROGRAMMING
VECTOR PROCESSING