VLSI design of a single chip reed-solomon encoder
Technical Report
·
OSTI ID:6729280
A design for a single chip implementation of a Reed-Solomon encoder is presented. The architecture that leads to this single VLSI chip design makes use of a bit serial finite field multiplication algorithm.
- Research Organization:
- Jet Propulsion Lab., Pasadena, CA (USA)
- OSTI ID:
- 6729280
- Report Number(s):
- N-83-14993/0
- Country of Publication:
- United States
- Language:
- English
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