On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays

Journal Article · Sat Oct 01 00:00:00 EDT 1988 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.5988· OSTI ID:6508779

Shao, H M ^[1]; Reed, I S ^[2]

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1. Aerospace Corp., Los Angeles, CA (US)
2. Dept. of Electrical Engineering, Univ. of Southern California, Los Angeles, CA (US)

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous paper is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure correction capability is also incorporated with little additional complexity. By using a multiplexing technique, a new implementation of Euclid's algorithm maintains the throughput rate with less circuitry. Such improvements result in both enhanced capability and significant reduction in silicon area, therefore making it possible to build a pipeline Reed-Solomon decoder on a single VLSI chip.

• OSTI ID: 6508779
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:10; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
DATA PROCESSING
DESIGN
ELEMENTS
GRASS
LILIOPSIDA
MAGNOLIOPHYTA
MATHEMATICAL LOGIC
PIPELINES
PLANTS
PROCESSING
REEDS
SEMIMETALS
SILICON