Design and implementation of a single-chip 1-d median filter
Technical Report
·
OSTI ID:6736265
The design and implementation of a 1-Dimensional median filter in VLSI is presented. The device is designed to operate an 8-bit sample sequences with a window size of 5 samples. Extensive pipelining and employment of systolic concepts at the bit level enable the chip to filter at rates up to 10 Mega-samples per second. The chip is designed to be implemented with a lambda = 2.5 micro NMOS technology and is 6.2 mm by 5.0 mm in size. A circuit configuration for using the chip in approximate 2-D median filtering is also presented.
- Research Organization:
- Carnegie-Mellon Univ., Pittsburgh, PA (USA). Dept. of Computer Science
- OSTI ID:
- 6736265
- Report Number(s):
- AD-A-123328/7
- Country of Publication:
- United States
- Language:
- English
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